Job Description: Title: Design Verification Engineers req for full chip verification Role and Responsibilities: Individual contributor to verify the IPs at full chip level Skill Requirements: Experience in HVL (SV-UVM) based Design verification, Experts in assertion checks, Implementing & closing functional coverage, code coverage. Good to have: Understanding of Display protocol, Exposure to serial protocols Experience: Minimum 10+ years of experience 

Qualifications: B.Tech/B.E/M.Tech/M.E