About SiTime

 

SiTime Corporation is the precision timing company. Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power and better reliability. With more than 3 billion devices shipped, SiTime is changing the timing industry. For more information, visit www.sitime.com.

Job Summary

The Sr. Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits. The Sr. Layout Design Engineer will review, and coordinate work content performed by offshore layout designers.  Train junior layout engineers and offshore layout contractors.  Contribute to develop standard layout methodologies across site.  Contribute to build process and procedures to achieve high layout quality

Responsibilities:

Requires remote interfacing with local and global design and layout teams in multiple design centers across different time zonesLead Top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOS circuitsPerform schematic-driven layout and design constraintsDesign die-area efficient layouts according to circuit designer requirementsPerform block or top-level layout designsPerform floor-planning, power line planning, shielding, and device-matching layoutVerify layouts. Pass DRC, LVS, and ERCContribute to various chip-level routing and layout needsPerform chip level integration, verifications, and tape-outSupport other projects as needed by managementTrain junior layout engineers and offshore layout contractorsContribute to develop common best practices and workflow across all sites Contribute to build process and procedures to achieve high layout quality

Qualifications & Requirements:

AA/AS Degree in Layout Design or related field or equivalent experience10 years’ experience with layout design for analog and full-custom digital blocksExperience TSMC 180nm, 65nm, 22nm process technologiesProficient in using layout editing tools in the Cadence Virtuoso design environmentSolid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor CalibreConceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolationStrong capability of solving device matching, electro-migration, signal integrity and power distribution problems while meeting area constraintsExperience in chip‐level floor planning and analog block integrationExperience chip level integration, verifications, and tape-outAbility to use productivity‐enhancing tools and design scripts to further automate tasks is also desirableMust be able to lift, push, and pull up to 5 lbs.

Desired Characteristics & Attributes:

Attention to detail, organized, accurate and can produce efficient layout techniquesHas a good track record of on time work deliveryHas a self-motivated, team player with good communication skillsAbility to work well with others in a fast-paced collaborative team environment

At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent. In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.

SiTime is an Equal Opportunity Employer. We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verify program.

Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique. 

Innovation on Top – Philosophies of Innovation with Rajesh VashistFabrication Knowledge – An Interview with Rajesh VashistSiTime Corporation – YouTube

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