Founded in 2016, we are a Series C semiconductor startup with over $300M in funding, developing a next-generation processor designed to unify traditionally separate computing domains-AI, HPC, and cloud workloads-into a single architecture that significantly enhances performance and energy efficiency.

We are actively hiring Senior Design Engineers who are either local or open to relocating to the Bay Area or Las Vegas, with the expectation of working onsite in a hybrid capacity. Our processor is currently in the final stages of design, with tape-out anticipated soon and commercial availability projected within the next couple of years. The architecture features a multi-chiplet design with hundreds of cores per chiplet, and early benchmarks suggest performance gains far exceeding those of today's leading processors.

We're looking for engineers with expertise in any of the following areas:

Processor & Architecture Expertise

Deep knowledge of ARM and x86 architectures, multicore and multiprocessor systems, including consistency protocols and coherence mechanismsStrong understanding of computer architecture, pipeline design, and high-speed, low-power processor pipelines for ASICs, SoCs, and multi-core systemsExperience with high-performance L2 cache units, cache controller design, cache hierarchy, and coherency protocolsFamiliarity with microprocessor cache systems and embedded logic analyzersBackground in large-scale ASIC design and low-power logic design using deep submicron technologies

Digital & RTL Design Flow

Proficiency in digital design from architecture through RTL, verification, synthesis, and static timing analysis (STA)Skilled in Verilog/SystemVerilog, CDC, LINT, and synthesis tools

FPGA & Protocol Integration

Experience with FPGA design, architectural concept development, integration, and debuggingStrong familiarity with protocols such as PCIe, Ethernet (100G+), and DDR4

Specialized Functional Units & Algorithms

Experience designing Arithmetic Logic Units (ALUs) with a focus on high-speed processor pipelinesExpertise in fetch unit architecture for both general-purpose and AI processing needsKnowledge of branch prediction algorithms and instruction fetch design for high-performance microprocessorsHands-on experience implementing, debugging, and optimizing high-performance MMU/TLB subsystems for advanced processor architectures

Memory Interface & Error Correction

Background in DRAM interface design and advanced DRAM control block enhancementsExperience with RS and BCH error correction codes

Benefits

Competitive salary and benefits package + stock options Relocation assistanceOpportunities for professional development and advancementInternational environment and further career progressionGetting in touch with bleeding-edge technologyFlexible working hours with work-life balanceCollaborative and supportive work environmentAbility to work from home (must reside in the Bay Area or Las Vegas to meet with the team as needed)