8+ years of experience in system-level modeling or SoC design Strong proficiency in SystemC and C++

Hands-on experience with TLM 2.0 modeling

Solid understanding of SoC architecture, buses (AXI, AHB), memory systems, and interconnects

Experience with hardware/software co-design and co-simulation

Familiarity with simulation tools (e.g., Synopsys Virtualizer, Cadence Virtual System Platform, or similar)

Strong debugging and problem-solving skills

Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or related field