This is a hybrid role with four days per week at Cisco’s Yerevan office.

Meet the Team

Join Cisco’s CHG Team in Armenia, a leader in physical design and implementation for groundbreaking networking chips under the globally recognized Silicon One brand. Our team focuses on advancing chip-level implementation and analysis for innovative technologies, employing advanced methodologies and best-in-class tools to solve large-scale design challenges. As a part of this innovative team, you’ll lead and collaborate on the physical implementation and sign-off of high-complexity silicon, ensuring the performance, reliability, and quality of the technology that powers tomorrow’s connectivity. Together, we are redefining what’s possible in networking technology.

Your Impact

As a Physical Design Technical Leader in Cisco’s Silicon One development, you will take end-to-end technical ownership of block-level physical implementation, driving the flow from RTL to tape-out. You will apply deep expertise in synthesis, place-and-route, timing closure, and sign-off to deliver high-quality, production-ready designs that meet performance, power, and area goals.

You will work closely with frontend, IP, CAD, and tool vendor teams across global locations to resolve implementation challenges and ensure seamless integration. In this role, your focus is on providing technical direction, hands-on problem solving, and advancing physical design methodologies that enable next-generation networking silicon.

Execute and own block-level physical implementation from RTL through GDSII and tape-out.

Perform synthesis, floorplanning, place-and-route, timing closure, physical verification, and sign-off analysis.

Ensure designs meet PPA (performance, power, area) requirements and interface cleanly with related blocks and system-level constraints.

Partner with cross-functional teams to debug complex issues, align on design requirements, and deliver optimized solutions.

Lead technical investigations, propose improvements, and contribute to methodology enhancements for physical design flows.

Provide technical guidance and knowledge sharing to peers, fostering a collaborative and innovative engineering environment.

Minimum Qualifications

Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.

8+ years of experience in ASIC design and physical implementation, including verification.

Deep expertise with deep submicron CMOS technologies.

Extensive knowledge of the full design cycle from RTL to GDSII.

Strong understanding of Static Timing Analysis, timing closure, and design constraints.

Proven skills in block-level synthesis, place and route, and timing closure.

Familiarity with industry-standard physical design and sign-off tools.

Excellent verbal and written communication skills in English.

Preferred Qualifications

Direct experience with EM/IR and ESD analysis, including debugging and solution development.

Proficiency in scripting languages such as Tcl, Python, or Shell to improve design flow efficiency.

Experience collaborating with global teams and vendor partners.

Demonstrated ability to mentor team members and foster a collaborative environment.

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you.