Job Description

As a Graduate Digital Backend Engineer, you will participate in the end‑to‑end physical implementation of complex SoC and mix-signal designs. You will work within an experienced backend team and learn how to transform RTL code into a tape‑out‑quality GDSII database using the Cadence digital implementation tool suite. The role spans the complete backend flow including synthesis, floorplanning, power planning, place & route, timing closure, physical verification, and sign‑off.

You will receive structured coaching, access to internal training material, and the opportunity to work on real production designs while gradually taking ownership of specific blocks.

 

1. RTL Synthesis (Cadence Genus)

Run logic synthesis and generate optimized netlists according to timing, area, and power constraints.Perform constraint development and validation (SDC).Analyze synthesis reports: timing, area, power, QoR, and identify optimization opportunities.Collaborate with RTL and verification teams to resolve structural issues.

2. Floorplanning & Power Planning (Cadence Innovus)

Assist in creating initial chip and block floorplans, including die/core sizing, aspect ratio, macro placement, and I/O planning.Support power grid (PG) design, power rail planning, and IR‑drop‑aware placement.Ensure integration of physical IP (memories, analog blocks, hard macros).

3. Placement, Clock Tree Synthesis & Routing

Run placement, CTS, and detailed routing using Cadence Innovus.Perform optimization iterations for timing, congestion, and power.Implement design‑for‑manufacturability (DFM) and power‑intent (UPF) guidelines.Ensure correctness of CTS: skew, slew, balancing, and power efficiency.

4. Static Timing Analysis (Cadence Tempus)

Analyze and resolve setup/hold violations across multiple modes and corners.Work with multi‑corner, multi‑mode (MCMM) analysis environments.Debug timing paths, parasitics, and cross‑talk using Cadence sign‑off flows.

5. Power & IR‑Drop Analysis (Cadence Voltus)

Prepare power models and scenarios for dynamic and static IR‑drop analysis.Perform EM/IR validation and support PDN optimization.Interpret results and propose improvements in PG design or standard‑cell usage.

6. Physical Verification (Mentor Calibre)

Run DRC, LVS, and ERC checks on full layouts.Debug physical verification violations and collaborate with layout engineers.Ensure the design meets manufacturing requirements and PDK guidelines.

7. Sign‑off, ECO Handling & Final GDSII Output

Execute ECO cycles using Cadence Innovus/Genus ECO flows.Validate timing, power, signal integrity, and physical verification after ECOs.Prepare the final, tape‑out‑ready GDSII database.Support documentation and sign‑off reviews for tape‑out

 

Qualifications
Master’s or Bachelor’s degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field.Solid understanding of CMOS fundamentals, digital design, and VLSI basics.Familiarity with Verilog/VHDL, SDC constraints, and Unix/Linux workflows.Basic exposure to scripting languages (TCL, Python, or Perl).Strong analytical thinking and problem‑solving skills.Proactive, collaborative, and eager to learn.

Nice‑to‑Have Skills

Knowledge of RTL synthesis or P\&R concepts through academic projects or internships.Understanding of timing analysis, STA concepts, or physical verification.Experience with any EDA tool (Cadence, Synopsys, Mentor).

What We Offer

Structured onboarding and mentorship by experienced Senior Engineers.Hands‑on work on real production ASICs/SoCs.Access to industry‑standard EDA tools (Cadence Genus/Innovus/PrimeTime).Career growth path toward Physical Design Engineer or Implementation Lead.Opportunity to contribute to tape‑outs across multiple technology nodes.
Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.
 
With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’     
 
At Renesas, you can: 

Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.    

Are you ready to own your success and make your mark?  

Join Renesas. Let’s Shape the Future together.  

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

We have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.